Digital Computer Fundamentals
1. **State De Morgan's law.**
De Morgan's laws are two transformation rules that are useful in Boolean algebra and set theory. They state:
$$\overline{A \cdot B} = \overline{A} + \overline{B}$$
$$\overline{A + B} = \overline{A} \cdot \overline{B}$$
This means the complement of a product is the sum of the complements, and the complement of a sum is the product of the complements.
2. **Define the term "minterm".**
A minterm is a product (AND) term in Boolean algebra that includes all variables in the function, each appearing exactly once, either complemented or uncomplemented. It represents a single combination of variables that makes the function true.
3. **Convert (231.25)₁₀ to binary number.**
Step 1: Convert integer part 231 to binary:
$231 \div 2 = 115$ remainder $1$
$115 \div 2 = 57$ remainder $1$
$57 \div 2 = 28$ remainder $1$
$28 \div 2 = 14$ remainder $0$
$14 \div 2 = 7$ remainder $0$
$7 \div 2 = 3$ remainder $1$
$3 \div 2 = 1$ remainder $1$
$1 \div 2 = 0$ remainder $1$
Reading remainders from bottom to top: $11100111_2$
Step 2: Convert fractional part 0.25 to binary:
Multiply by 2: $0.25 \times 2 = 0.5$, bit = 0
Multiply fractional part 0.5 by 2: $0.5 \times 2 = 1.0$, bit = 1
Fractional binary is $0.01$
Final binary number: $231.25 = 11100111.01_2$
4. **Use 1's complement technique to perform $(1001)_2 - (1111)_2$.**
Step 1: Find 1's complement of subtrahend (1111):
Complement of $1111$ is $0000$
Step 2: Add minuend and 1's complement of subtrahend:
$1001 + 0000 = 1001$
Step 3: Since no carry out, take 1's complement of result:
Complement of $1001$ is $0110$
So, the result is $-0110_2$ (negative sign shows subtraction result is negative).
5. **Minimize the Boolean function:**
$$F= (A + B' + C')(A + B' + C)(A + B + C')$$
Use distributive and absorption laws:
Notice common term $A$ in all; rewrite:
Since $A$ appears in all sums, expand combination only for the parts without $A$ would be unnecessary; instead simplify each term:
Since $A + B' + C'$ and $A + B' + C$ differ by $C$ only, their AND simplifies:
$$(A + B' + C')(A + B' + C) = A + B'$$
(Using consensus theorem)
Now multiply with the third term:
$$(A + B')(A + B + C')$$
Distribute:
$= A(A + B + C') + B'(A + B + C')$
$= A + B' A + B' B + B' C'$
Simplify terms:
$B' A$ is $A B'$, $B' B = 0$, so:
$= A + A B' + 0 + B' C'$
Since $A + A B' = A$ (absorption law),
Final simplified function:
$$F = A + B' C'$$
6.
(i) **Implement NAND using NOR gate:**
NAND operation is the complement of AND: $\overline{AB}$
Using NOR gates, NAND can be implemented by applying De Morgan's law:
$$\overline{A B} = \overline{\overline{\overline{A} + \overline{B}}}$$
So,
- First NOR gate to get $\overline{A}$: NOR A with A
- Second NOR gate to get $\overline{B}$: NOR B with B
- Third NOR gate to get $\overline{A} + \overline{B}$ NORed: output is $\overline{\overline{A} + \overline{B}} = A B$
- NAND is complement of AND, so feeding the AND output to NOT (NOR gate with same input) gives NAND.
(ii) **Implement XOR gate using NAND gate:**
XOR can be expressed as:
$$A \oplus B = (A \cdot \overline{B}) + (\overline{A} \cdot B)$$
Using NAND gates only, XOR can be constructed as:
$$X = ((A \text{ NAND } B) \text{ NAND } (A \text{ NAND } (A \text{ NAND } B))) \text{ NAND } ((B \text{ NAND } (A \text{ NAND } B)) \text{ NAND } (B \text{ NAND } (A \text{ NAND } B)))$$
This is a standard NAND gate XOR implementation.
7. Circuit design for counting number of 1's in 3-bit input A, B, C with outputs X and Y:
7a. **Complete the truth table:**
| A | B | C | Number of 1's | X | Y |
|---|---|---|---------------|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 2 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 2 | 1 | 0 |
| 1 | 1 | 0 | 2 | 1 | 0 |
| 1 | 1 | 1 | 3 | 1 | 1 |
7b. **Expression for X and Y:**
X represents the high bit and Y the low bit in binary count of 1's.
From the table:
- $X = 1$ when number of 1's is 2 or 3. Boolean expression:
$$X = (A \cdot B) + (B \cdot C) + (A \cdot C)$$
- $Y = 1$ when number of 1's is odd (1 or 3), which is the XOR of inputs:
$$Y = A \oplus B \oplus C$$
7c. **Minimize X and Y using 3-variable Karnaugh Map:**
- For $X$:
KMap for $X$ shows 1s in cells with 2 or 3 ones.
Simplified expression using KMap is:
$$X = AB + BC + AC$$
(This is already minimal.)
- For $Y$:
$Y$ is the parity of inputs, the XOR of three variables. Minimal form:
$$Y = A \oplus B \oplus C$$
7d. **Implement circuit:**
- $X$ can be implemented using three 2-input AND gates and one 3-input OR gate (or chained OR gates):
$X = (A \cdot B) + (B \cdot C) + (A \cdot C)$
- $Y$ can be implemented with two XOR gates:
First XOR: $D = A \oplus B$,
Second XOR: $Y = D \oplus C$
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