1. **Problem Statement:** Design a combinational circuit whose input is a 4-bit binary number in 4, 4, 3, -2 code and the output is in 5, 4, 2, 1 code. 2. **Understanding the Codes:** - Input code digits are weighted as 4, 4, 3, -2. - Output code digits are weighted as 5, 4, 2, 1. 3. **Step 1: Express the input number in decimal form:** Let the input bits be $A, B, C, D$ corresponding to weights 4, 4, 3, -2 respectively. The decimal value of input is: $$\text{Input} = 4A + 4B + 3C - 2D$$ 4. **Step 2: Express the output number in decimal form:** Let the output bits be $W, X, Y, Z$ corresponding to weights 5, 4, 2, 1 respectively. The decimal value of output is: $$\text{Output} = 5W + 4X + 2Y + Z$$ 5. **Step 3: Equate input and output decimal values:** $$4A + 4B + 3C - 2D = 5W + 4X + 2Y + Z$$ 6. **Step 4: Determine output bits $W, X, Y, Z$ as functions of input bits $A, B, C, D$:** - Since the input and output represent the same number, the output bits must encode the input value in the new code. - To find the Boolean expressions for $W, X, Y, Z$, list all possible input combinations (16 total) and compute the decimal value. - Then convert that decimal value to the output code digits. 7. **Step 5: Construct truth table:** | A | B | C | D | Input Value | Output Value | W | X | Y | Z | |---|---|---|---|-------------|--------------|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | -2 | (invalid) | | | | | | ... | ... | ... | ... | ... | ... | ... | ... | ... | ... | - Note: Negative input values may be invalid or require special handling. 8. **Step 6: Simplify and derive Boolean expressions:** - Use Karnaugh maps or Boolean algebra to simplify each output bit function. 9. **Step 7: Implement the circuit:** - Use logic gates (AND, OR, NOT) to realize the simplified Boolean expressions for $W, X, Y, Z$. **Final answer:** The design involves creating a truth table mapping input bits $A,B,C,D$ with weights 4,4,3,-2 to output bits $W,X,Y,Z$ with weights 5,4,2,1, then deriving Boolean expressions for each output bit and implementing them with logic gates. This completes the detailed solution for the first question.